1. Field of the Invention
The present invention relates to an image display apparatus, to a timing controller for a driver IC, and to a source driver IC. More particularly, the invention relates to improvement of an image display apparatus, such as a liquid crystal display, having a timing controller to generate a control signal, a driver IC to take in image data and to supply the image data to a source line, and a display panel for screen-displaying the image data supplied to the source line.
2. Description of the Related Art
An image display apparatus, such as a liquid crystal display, causes a source driver IC to take in image data according to operating clocks and supply the image data to each of source lines thereby to perform screen-displaying. Control signals, such as an operating clock, and image data are supplied from a timing controller. In such an image display apparatus, sometimes, the wiring between the timing controller and the source driver IC is shortcircuited according to the position, at which each of the timing controller and the source driver IC is mounted, and to the assignment of image data to each of data input ports of the source driver IC. Thus, through holes for electrically connecting a surface layer wiring to a lower layer wiring are provided in a board so as to prevent the wiring from being shortcircuited.
FIG. 7 is a schematic view showing the configuration of an image display apparatus. This figure shows a liquid crystal module 100 including a substrate 101, on which a display panel 102, a source driver IC 103, and a gate driver IC 104 are provided, and also including a board 107 on which a timing controller 108 is provided. The display panel 102 is a liquid crystal panel to perform screen-displaying according to image data supplied to signal lines (or source lines) 105. The source lines 105 and the gate lines 106 are formed in a matrix-like configuration thereon. Plural source driver ICs 103 are provided along one side of the display panel 102 on the substrate 101, and plural gate driver ICs 104 are provided along an adjacent side of the display panel 102 thereon.
The timing controller 108 outputs control signals, such as an operating clock for horizontal scanning, and a horizontal synchronization start pulse, to each of the source driver ICs 103, and also outputs control signals, such as an operating clock for vertical scanning, and a vertical synchronization start pulse, to each of the gate driver ICs 104.
FIG. 8 is a view illustrating the details of a primary part of a conventional image display apparatus and shows the manner of a wiring between the timing controller 108 and each of the source driver ICs 103. Each of the source driver ICs 103 is provided with plural data input ports to take in image data, and with a clock port to which operating clocks are inputted. Surface layer wirings extend from teach of the data input ports and the clock port. Among the source driver ICs 103, associated data input ports and associated clock ports are electrically connected to one another through the through hole and the lower layer wiring so as to prevent the wirings from being shortcircuited.
Incidentally, the image data and the operating clocks are assumed to be transmitted from a CMOS (Complementary Metal Oxide Semiconductor) gate by a single-end transmission. Two groups of the data input ports are disposed in such a way as to be symmetrical with respect to the clock port. That is, the group of the data input ports, to which image data EVEN000R to EVEN023B are inputted, and that of the data input ports, to which image data ODD000R to ODD023B are inputted, are disposed on either side of the clock port CLK.
The timing controller 108 is provided with plural data output ports to output image data, and with a clock port to output operating clocks. Surface layer wirings extend from each of the data output ports and this clock port. In a case where the order of arrangement of the ports of the timing controller 108, which respectively associated with the image data EVEN000R to EVEN023B and ODD000R to ODD023B, is the same as that of arrangement of the ports of each source driver IC 103, which are respectively associated with such image data, and where the timing controller 108 is disposed in such a way as to be opposed to each of the source drive ICs 103, the surface layer wirings drawn from the timing controller 108 toward the source driver ICs 103 intersect with one another on the surface layer and are shortcircuited. Thus, through holes are newly provided in the board, and the associated ones of the lower layer wirings are connected to each other.
Consequently, even in the case where the timing controller 108 having the ports, the order of arrangement of which are respectively associated with the image data EVEN000R to EVEN023B and ODD000R to ODD023B and is the same as that of arrangement of the ports of each source driver IC 103, which are respectively associated with such image data, and where the timing controller 108 is disposed in such a way as to be opposed to the source drive IC 103, the timing controller 108 can be connected to the source drive IC 103 without shortcircuiting. However, because of the increase in the number of through holes, it is necessary for preventing occurrence of shortcircuiting to increase wiring spacing. Thus, such a conventional image display apparatus has the problems that the area of the circuit board increases, and that the multilayering thereof occurs. Further, when the number of through holes in a transmission path increases, the number of points of discontinuity in the characteristic impedance of the transmission path increases. Consequently, the conventional image display apparatus has the problem that the quality of waveform of a signal is deteriorated during the transmission of image data.
Thus, to properly connect the timing controller to the source driver IC without newly providing through holes therein, it is considered that the order of arrangement of image data outputted from the data output ports of the timing controller is inverted as need arises.
FIG. 9 is a view illustrating the details of a primary part of a conventional image display apparatus and shows the manner of wiring between a timing controller 110 and the source driver IC by inverting the order of arrangement of image data to thereby supply the data to the data output ports. This timing controller 110 can invert the order of arrangement of image data and output such image data to the data output ports. Therefore, the inversion of the order of arrangement of the image data enables the appropriate connection between each port of the timing controller 110 and an associated port of the source driver IC 103 through the use of the surface layer wiring without newly providing through holes even in the case where the timing controller 110 is disposed in such a way as to be opposed to the source drive IC 103. However, the image display apparatus has the problem that in a case where the groups of the data input ports are arranged in such a manner as to be asymmetrical with respect to the clock port, even when the order of arrangement of the image data is inverted, the associated ports cannot properly be connected to each other unless through holes are newly provided therein.
In a case where the image data and the operating clock are transmitted in the form of differential signals by using RSDS (Reduced Swing Differential Signaling), usually, the arrangement of image data taken in from the data input ports of the source driver IC are asymmetrical with respect to the clock port. In such a case, even when the image data are supplied to the data output ports by inverting the order of the arrangement of the image data in the timing controller, the clock port of the timing controller cannot appropriately be connected to the clock port of the source driver IC unless through holes are newly provided, because the arrangement of the groups of data output ports are not symmetrical with respect to the clock port.
FIG. 10 is a view illustrating the details of a primary part of a conventional image display apparatus and shows the manner of wiring between a timing controller 121 and each of source driver ICs 120 so that the arrangement of image data taken in from data input ports is asymmetrical with respect to the clock port. Two groups of the data input ports are provided in each source driven IC 120 in such a way as to be asymmetrical with respect to the clock port. That is, the group of the data input ports, to which image data D000N to D003P are inputted, and the group of the data input ports, to which image data D010N to D013P and D020N to D023P are inputted, are disposed on either side of a group of clock ports CLKN and CLKP.
The order of arrangement of the ports of the timing controller 121 is the same as that of arrangement of the ports of each of the source driver ICs 120. The timing controller 121 is placed by being opposed to the source driver IC 120. Further, the ports of the timing controller 121 are connected to those of the source driver IC 120 by newly providing through holes and by using the lower layer wirings. In such an image display apparatus, even when the order of arrangement of image data outputted from the data output ports of the timing controller 121 is inverted so as to reduce the number of through holes, the associated clock ports cannot be connected to each other unless through holes are provided, because the arrangement of the groups of the data output ports are not symmetrical with respect to the group of the clock ports. (See JP-A-2002-91367.)
As described above, the conventional image display apparatus has the problem that in the case where the timing controller is connected to the source driver IC without shortcircuiting the wirings, the area of the circuit board increases, and the multilayering thereof occurs. Particularly, the conventional image display apparatus has the problems that the number of points of discontinuity in the characteristic impedance of the transmission path increases, and that the quality of waveform of a signal is deteriorated.
Also, the conventional image display apparatus has the problem that in a case where the groups of the data input ports are disposed in each of the source driver ICs in such a way as to be asymmetrical with respect to the clock port, the associated ports of the timing controller and the source driver IC cannot appropriately be connected to each other unless through holes are newly provided, even when the image data are supplied to the data output ports by inverting the order of arrangement of the image data of each group is inverted in the timing controller.